Science/Engineering System-On-Chip Test Architectures : Nanometer Design for Testability (012373973X)

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Author: Laung-Terng Wang, Charles E. Stroud, Nur Touba
Publisher: Elsevier Science & Technology
Publish Date: 2007
ISBN: 012373973X
Pages: 896

The same book is also published under the Morgan Kaufmann imprint. This book is a new book which deals with VLSI system-on-chip testing.

Taken from amazon.com:

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost.

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES

* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.

* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.

* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.

* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.

* Practical problems at the end of each chapter for students.

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2.5 out of 5 by Book123

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	Science/Engineering System-on-Chip Test Architectures (Systems on Silicon) Laung-Terng Wang, Charles E. Stroud, Nur A. Touba, "System-on-Chip Test Architectures (Systems on Silicon)"Publisher: Morgan Kaufmann \| Pages: 896 \| Date: 2007-11-16 \| ISBN: 012373973X \| PDF \| 8.77 MbModern electronics testing has a legacy ...
	VLSI Test Principles and Architectures: Design for Testability Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen, "VLSI Test Principles and Architectures: Design for Testability" Morgan Kaufmann \| 2006-07-07 \| ISBN: 0123705975 \| 808 pages \| PDF \| 4,9 MB This book is a comprehensive guide to new DFT meth ...
	Science/Engineering System-Level Modeling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures Gakgan Erbas, "System-Level Modeling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures" Amsterdam University Press \| 2006 \| ISBN: 9056294555 \| 154 pages \| PDF \| 1,6 MB System-level,modeling,design,exp ...
	System-on-a-Chip: Design and Test System-on-a-Chip: Design and TestISBN: 1580531075 Publisher: Artech House Publishers Author: Rochit RajsumanDescription:Starting with a basic overview of system-on-a-chip (SoC) including definitions of related terms, this text explains ...
	Technical System-on-Chip Test Architectures Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased per ...
	VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon) VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)ISBN: 0123705975 Publisher: Morgan Kaufmann Author: Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing WenDescription:This book is a comprehensive guide to new DFT ...

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Science/Engineering System-On-Chip Test Architectures : Nanometer Design for Testability

The same book is also published under the Morgan Kaufmann imprint. This book is a new book which deals with VLSI system-on-chip testing.

Taken from amazon.com:

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