Technical CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test (Frontiers in Electronic Testing) (Frontiers in Electronic Testing) (1402083629)

Like Book123?! Give us +1

Author: Manoj Sachdev, Andrei Pavlov

Publisher: Springer (2008)

Binding: Hardcover, 212 pages

pricer: $149.00

ISBN-10: 1402083629

editorialreviews

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

Buy Book at Lowest Price on Amazon

checked

Rating:
2.5 out of 5 by Book123

Download Links
Server	Status
Direct Download Link 1	Alive
Direct Download Link 2	Alive
Download Link (Download Link 1)	Alive
Download Link (Download Link 1)	Alive
Download Link (Download Link 1)	Alive
Buy This Book at Best Price >>

Like this article?! Give us +1:

	Science/Engineering Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing) Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits (Frontiers in Electronic Testing) By: Manoj Sachdev José Pineda de Gyvez ISBN-10: 0387465464 ISBN-13: 9780387465463 Publisher: Springer - 2007-06-21Hardcover \| 2nd ed. Edition ...
	Science/Engineering Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing) ===Electronic相关链接===Everyday Practical Electronic Magazine - All 20...[2007/1005]Everyday Practical Electronic - October 2007[2007/1003]Solution Manuals for Fundamentals of Quantum Me...[2007/1002]Penguin Dictionary Of Electronics[2007/ ...
	Science/Engineering CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test Andrei Pavlov, Manoj Sachdev “CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test" Springer \| 2008-06 \| ISBN: 1402083629 \| 200 pages \| PDF \| 5 MB /Thanks to gigapedia.org
	Science/Engineering A Designer's Guide to Built-in Self-Test (Frontiers in Electronic Testing) A Designer's Guide to Built-in Self-Test (Frontiers in Electronic Testing)Springer \| ISBN: 1402070500 \| 2002-05-31 \| PDF \| 344 pages \| 15 Mb A recent technological advance is the art of designing circuits to test themselves, referred to as ...
	Science/Engineering CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM ce ...
	High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test (Frontiers in Electronic Testing) Author: R. Dean AdamsPublisher: Springer (2002)Binding: Hardcover, 268 pagespricer: $149.00ISBN-10: 1402072554editorialreviews Based on the author's 20 years of experience in memory design, memory reliability development and memory test. Wr ...

Share this page with your friends now!
Text link
Forum (BBCode)
Website (HTML)

DISCLAIMER:

This site does not store Technical CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test (Frontiers in Electronic Testing) (Frontiers in Electronic Testing) on its server. We only index and link to Technical CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test (Frontiers in Electronic Testing) (Frontiers in Electronic Testing) provided by other sites. Please contact the content providers to delete Technical CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test (Frontiers in Electronic Testing) (Frontiers in Electronic Testing) if any and email us, we'll remove relevant links or contents immediately.

Book123

Categories

Share With Friends

Archive by Date

Search Tag

Newest

Useful Links

Technical CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test (Frontiers in Electronic Testing) (Frontiers in Electronic Testing)

Related Articles

DISCLAIMER:

Comments (0) All