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Science/Engineering Routing Congestion in VLSI Circuits: Estimation and Optimization

Posted on 2010-03-15




Name:Science/Engineering Routing Congestion in VLSI Circuits: Estimation and Optimization
ASIN/ISBN:0387300376
Language:English
File size:2 Mb
Publisher: Springer
Pages: 250
Publish Date: 2007-04-18
ISBN: 0387300376
File Type: PDF
File Size: 2 MB
   Science/Engineering Routing Congestion in VLSI Circuits: Estimation and Optimization

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Routing Congestion in VLSI Circuits: Estimation and Optimization

Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design.

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