Technical The Art of Verification with SystemVerilog Assertions (0971199418)

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Technical The Art of Verification with SystemVerilog Assertions

Posted on 2010-04-11

Name:	Technical The Art of Verification with SystemVerilog Assertions
ASIN/ISBN:	0971199418
Language:	English
File size:	2 Mb

Technical The Art of Verification with SystemVerilog Assertions

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Highlights include: Teaches the SVA lanaguage using simple easy-to-understand language. Teaches SVA semantics by examples. Detailed discussion of SVA and assertion-based verification Identifying design areas that need assertions Applying SVA assertions to both simulation- and formal Practical issues with SVA Â¿ Describing design behavior in SVA Â¿ Verifying protocol conformity Â¿ Verifying data integrity Â¿ Developing an effective functional coverage strategy The Art of Verification with SystemVerilog Assertions (SVA) covers the essential elements of SVA with numerous, detailed examples. The book demonstrates how SVA can be harnessed to implement effective, assertion-based verification. It teaches the SVA language by explaining its usage in the context of practical verification issues. SVA syntax and features are explained in a simple and very easy-to-understand language. The usage of each construct is illustrated with both simple examples and examples drawn from common verification problems. After SVA syntax and semantics are covered, they are used to develop an effective, assertion-based verification strategy for a real-world design.

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