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Valeria Bertacco, "Scalable Hardware Verification with Symbolic Simulation"

Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner workings of symbolic simulation. The core of this book focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them. In particular, it covers a range of solutions that exploit approximation and parametrization methods, including quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations based on disjoint-support decompositions. In structuring this book, the author’s hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research. Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field. Highlights: A discussion of the leading hardware verification techniques, including simulation and formal verification solutions Important concepts related to the underlying models and algorithms employed in the field The latest innovations in the area of symbolic simulation, exploiting techniques such as parametric forms and decomposition properties of Boolean functions Providing insights into possible new developments in the hardware verification

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