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Software Related Mentor Graphics ModelSim SE 6.5b

Posted on 2011-03-16




Name:Software Related Mentor Graphics ModelSim SE 6.5b
ASIN/ISBN:3540770917
File size:568.2 Mb
File Size: 568.2 MB
Other Info: Mentor Graphics ModelSim SE 6.5b
   Software Related Mentor Graphics ModelSim SE 6.5b

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The system of digital simulation projects based on VHDL, Verilog and "mixed" descriptions of built-in performance analysis, indicating "active" code (code coverage), the comparator time diagrams and visualizer Enhanced Dataflow Window. Main features: high speed simulation for RTL and Gate projects; single simulator kernel and optimized architecture Native Compiled; interactive debugging and analysis module Debug Detective; integrated analysis of Code Coverage; optimization speed simulation using Performance Analyzer Performance Analyzer; exhaustive tracing signals Signal Spy; debugger for C, C and interfaces support Tcl / Tk; support for OS Unix / Windows / Linux.

Key Features

Record-high speed compilation and simulation. Single "core" model. The possibility of modeling "mixed" VHDL / Verilog-projects on a single "core". Easy portability and support for libraries through the independence of the platform and version of the simulator. Protection of "intellectual property", which are guaranteed by compiling machine-independent object code. Extensive debugging capabilities. Simple and full-featured graphical user interface. Easy to configure to individual user requirements using Tcl / Tk. Paul

Nye supports all standard VHDL and Verilog. Support the library are all the major manufacturers of ASIC and FPGA. Integration with packages of other firms. Technical support firm Mentor Graphics. ModelSim SE / PLUS allows the user to "mix" VHDL-Verilog-and the objects within a project, enabling the cross-cutting debug the project.

ModelSim SE is our UNIX, Linux, and Windows-based simulation and debug environment, combining high performance with the most powerful and intuitive GUI in the industry.

ModelSim SE Features:

- Multi-language, high performance simulation engine

- Verilog, VHDL, SystemVerilog Design

- Code Coverage

- SystemVerilog for Design

- Integrated debug

- JobSpy Regression Monitor

- Mixed HDL simulation option

- SystemC Option

- TCL / tk

- Solaris and Linux 32 & 64-bit

- Windows 32-bit

Version: 6.5b

Developer: Mentor Graphics

Platform: Windows & Linux

Compatibility with Vista: Yes

Language: English Only

Medicine: Yes

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