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Science/Engineering Low-Power High-Speed ADCs for Nanometer CMOS Integration

Posted on 2010-03-15




Name:Science/Engineering Low-Power High-Speed ADCs for Nanometer CMOS Integration
ASIN/ISBN:1402084498
Language:English
File size:4 Mb
Publisher: Springer
Pages: 98
Publish Date: 2008-08-01
ISBN: 1402084498
File Type: PDF
File Size: 4 MB
   Science/Engineering Low-Power High-Speed ADCs for Nanometer CMOS Integration

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Low-Power High-Speed ADCs for Nanometer CMOS Integration

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested.

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