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Simulation-based versus formal verification: advantages, disadvantages, and tradeoffs

Coding for verification: functional and timing correctness, syntactical and structure checks, simulation performance, and more

Simulator architectures and operations, including event-driven, cycle-based, hybrid, and hardware-based simulators

Testbench organization, design, and tools: creating a fast, efficient environment

Test scenarios and assertion: planning, cases, generators, commercial and Verilog assertions, and more

Ensuring complete coverage, including code, parameters, functions, items, and cross-coverage

The verification cycle: failure capture, scope reduction, bug tracking, simulation data dumping, isolation of underlying causes, revision control, regression, release mechanisms, and tape-out criteria.

An accessible introduction to the mathematics and algorithms of formal verification, from Boolean functions to state-machine equivalence and graph algorithms

Decision diagrams, equivalence checking, and symbolic simulation

Model checking and symbolic computation .

Simply put, Hardware Design Verification will help you improve and accelerate your entire verification process& 8211;from planning through tape-out& 8211;so you can get to market faster with higher quality designs. .

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