Science/Engineering Design Verification with e (0131413090)

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Science/Engineering Design Verification with e

Posted on 2010-03-16

Name:	Science/Engineering Design Verification with e
ASIN/ISBN:	0131413090
Language:	English
File size:	1.83 Mb
ISBN:	0131413090
Publish Date:	2003
File Type:	CHM
Pages:	416 pages
File Size:	1.83 MB
Other Info:	Prentice Hall

Science/Engineering Design Verification with e

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Samir Palnitkar, «Design Verification with e»

E is a new Hardware Verification Language, or HVL. Verification is one of the most time consuming and cumbersome processes in hardware design. Design teams spend 50% to 70% of their time verifying designs, rather than creating new ones. As designs grow more complex, the verification problems increase exponentially - when a design doubles in size, the verification effort can easily quadruple. In the past design teams have used Verilog and VHDL. E gives engineers the speed and efficiency they have been craving, while also allowing for simulation of other components as well. This book emphasizes breadth rather than depth. It imparts to the reader a working knowledge of a broad variety of e-based topics, thus giving the reader a global understanding of e-based design verification. This book should be classified not only as an e book but, more generally, as a design verification book. Due to its popularity, it is likely that e will be standardized in the future.

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