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Technical CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Repost)

Posted on 2010-09-09




Name:Technical CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Repost)
ASIN/ISBN:1402083629
Publisher:Springer
Publish Date:edition 2008
Pages:212 pages
File size:10.6 Mb
Publisher: Springer
ISBN: 1402083629
Publish Date: edition 2008
File Type: PDF
Pages: 212 pages
File Size: 10,6 mb
   Technical CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Repost)

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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.

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