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ASIC and FPGA Verification

PART I INTRODUCTION 1

CHAPTER 1 INTRODUCTION TO BOARD-LEVEL VERIFICATION 3

1.1 Why Models are Needed 3

1.1.1 Prototyping 3

1.1.2 Simulation 4

1.2 Definition of a Model 5

1.2.1 Levels of Abstraction 6

1.2.2 Model Types 7

1.2.3 Technology-Independent Models 9

1.3 Design Methods and Models 10

1.4 How Models Fit in the FPGA/ASIC Design Flow 10

1.4.1 The Design/Verification Flow 11

1.5 Where to Get Models 13

1.6 Summary 14

CHAPTER 2 TOUR OF A SIMPLE MODEL 15

2.1 Formatting 15

2.2 Standard Interfaces 17

2.3 Model Delays 18

2.4 VITAL Additions 19

2.4.1 VITAL Delay Types 19

2.4.2 VITAL Attributes 20

2.4.3 VITAL Primitive Call 21

2.4.4 VITAL Processes 22

2.4.5 VitalPathDelays 24

2.5 Interconnect Delays 25

2.6 Finishing Touches 27

2.7 Summary 31

PART II RESOURCES AND STANDARDS 33

CHAPTER 3 VHDL PACKAGES FOR COMPONENT MODELS 35

3.1 STD_LOGIC_1164 35

3.1.1 Type Declarations 36

3.1.2 Functions 37

3.2 VITAL_Timing 37

3.2.1 Declarations 37

3.2.2 Procedures 38

3.3 VITAL_Primitives 39

3.3.1 Declarations 40

3.3.2 Functions and Procedures 40

3.4 VITAL_Memory 41

3.4.1 Memory Functionality 41

3.4.2 Memory Timing Specification 42

3.4.2 Memory_Timing Checks 42

3.5 FMF Packages 42

3.5.1 FMF gen_utils and ecl_utils 43

3.5.2 FMF ff_package 44

3.5.3 FMF Conversions 45

3.6 Summary 45

CHAPTER 4 AN INTRODUCTION TO SDF 47

4.1 Overview of an SDF File 47

4.1.1 Header 48

4.1.2 Cell 50

4.1.3 Timing Specifications 50

4.2 SDF Capabilities 52

4.2.1 Circuit Delays 52

4.2.2 Timing Checks 55

4.3 Summary 58

CHAPTER 5 ANATOMY OF A VITAL MODEL 59

5.1 Level 0 Guidelines 59

5.1.1 Backannotation 60

5.1.2 Timing Generics 60

5.1.3 VitalDelayTypes 61

5.2 Level 1 Guidelines 63

5.2.1 Wire Delay Block 63

5.2.2 Negative Constraint Block 65

5.2.3 Processes 65

5.2.4 VITAL Primitives 70

5.2.5 Concurrent Procedure Section 70

5.3 Summary 70

CHAPTER 6 MODELING DELAYS 73

6.1 Delay Types and Glitches 73

6.1.1 Transport and Inertial Delays 73

6.1.2 Glitches 74

6.2 Distributed Delays 75

6.3 Pin-to-Pin Delays 75

6.4 Path Delay Procedures 76

6.5 Using VPDs 82

6.6 Generates and VPDs 83

6.7 Device Delays 83

6.8 Backannotating Path Delays 88

6.9 Interconnect Delays 89

6.10 Summary 90

CHAPTER 7 VITAL TABLES 91

7.1 Advantages of Truth and State Tables 91

7.2 Truth Tables 92

7.2.1 Truth Table Construction 92

7.2.2 VITAL Table Symbols 92

7.2.3 Truth Table Usage 93

7.3 State Tables 97

7.3.1 State Table Symbols 97

7.3.2 State Table Construction 97

7.3.3 State Table Usage 98

7.3.4 State Table Algorithm 99

7.4 Reducing Pessimism 100

7.5 Memory Tables 101

7.5.1 Memory Table Symbols 101

7.5.2 Memory Table Construction 102

7.5.3 Memory Table Usage 103

7.6 Summary 105

CHAPTER 8 TIMING CONSTRAINTS 107

8.1 The Purpose of Timing Constraint Checks 107

8.2 Using Timing Constraint Checks in VITAL Models 108

8.2.1 Setup/Hold Checks 108

8.2.2 Period/Pulsewidth Checks 112

8.2.3 Recovery/Removal Checks 114

8.2.4 Skew Checks 117

8.3 Violations 121

8.4 Summary 122

PART III MODELING BASICS 123

CHAPTER 9 MODELING COMPONENTS WITH REGISTERS 125

9.1 Anatomy of a Flip-Flop 125

9.1.1 The Entity 125

9.1.2 The Architecture 129

x Contents

9.1.3 A VITAL Process 131

9.1.4 Functionality Section 133

9.1.5 Path Delay 134

9.1.6 The “B” Side 135

9.2 Anatomy of a Latch 137

9.2.1 The Entity 138

9.2.2 The Architecture 140

9.3 Summary 146

CHAPTER 10 CONDITIONAL DELAYS AND TIMING CONSTRAINTS 147

10.1 Conditional Delays in VITAL 147

10.2 Conditional Delays in SDF 149

10.3 Conditional Delay Alternatives 150

10.4 Mapping SDF to VITAL 152

10.5 Conditional Timing Checks in VITAL 153

10.6 Summary 156

CHAPTER 11 NEGATIVE TIMING CONSTRAINTS 157

11.1 How Negative Constraints Work 157

11.2 Modeling Negative Constraints 158

11.3 How Simulators Handle Negative Constraints 176

11.4 Ramifications 177

11.5 Summary 178

CHAPTER 12 TIMING FILES AND BACKANNOTATION 179

12.1 Anatomy of a Timing File 179

12.1.1 Header 179

12.1.2 Body 181

12.1.3 FMFTIME 181

12.2 Separate Timing Specifications 182

12.3 Importing Timing Values 183

12.4 Custom Timing Sections 183

12.5 Generating Timing Files 184

12.6 Generating SDF Files 184

12.7 Backannotation and Hierarchy 185

12.8 Summary 187

PART IV ADVANCED MODELING 189

CHAPTER 13 ADDING TIMING TO YOUR RTL CODE 191

13.1 Using VITAL to Simulate Your RTL 191

13.2 The Basic Wrapper 192

13.3 A Wrapper for Verilog RTL 206

13.4 Modeling Delays in Designs with Internal Clocks 206

13.5 Caveats 207

13.6 Summary 208

CHAPTER 14 MODELING MEMORIES 209

14.1 Memory Arrays 209

14.1.1 The Shelor Method 210

14.1.2 The VITAL_Memory Package 210

14.2 Modeling Memory Functionality 211

14.2.1 Using the Behavioral (Shelor) Method 211

14.2.2 Using the VITAL2000 Method 223

14.3 VITAL_Memory Path Delays 231

14.4 VITAL_Memory Timing Constraints 232

14.5 PreLoading Memories 235

14.5.1 Behavioral Memory PreLoad 235

14.5.2 VITAL_Memory PreLoad 237

14.6 Modeling Other Memory Types 238

14.6.1 Synchronous Static RAM 238

14.6.2 DRAM 241

14.6.3 SDRAM 244

14.7 Summary 249

CHAPTER 15 CONSIDERATIONS FOR COMPONENT MODELING 251

15.1 Component Models and Netlisters 251

15.2 File Contents 253

15.3 Generics Passed from the Schematic 253

15.3.1 Timing Generics 253

15.3.2 Control Generics 253

15.4 Integrating Models into a Schematic Capture System 254

15.4.1 Library Structure 254

15.4.2 Technology Independence 255

15.4.3 Directories 255

15.4.4 Map Files 256

15.5 Using Models in the Design Process 256

15.5.1 VHDL Libraries 257

15.5.2 Schematic Entry 257

15.5.3 Netlisting the Design 258

15.5.4 VHDL Compilation 258

15.5.5 SDF Generation 259

15.5.6 Simulation 261

15.5.7 Layout 261

15.5.8 Signal Analysis 262

15.5.9 Timing Backannotation 262

15.5.10 Timing Analysis 262

15.6 Special Considerations 262

15.6.1 Schematic Considerations 262

15.6.2 Model Considerations 263

15.7 Summary 266

CHAPTER 16 MODELING COMPONENT-CENTRIC FEATURES 269

16.1 Differential Inputs 269

16.2 Bus Hold 279

16.3 PLLs and DLLs 282

16.4 Assertions 284

16.5 Modifying Behavior with the TimingModel Generic 285

16.6 State Machines 285

16.7 Mixed Signal Devices 288

16.8 Summary 294

CHAPTER 17 TESTBENCHES FOR COMPONENT MODELS 295

17.1 About Testbenches 295

17.1.1 Tools 295

17.2 Testbench Styles 296

17.2.1 The Empty Testbench 296

17.2.2 The Linear Testbench 296

17.2.3 The Transactor Testbench 296

17.3 Using Assertions 297

17.4 Using Transactors 298

17.5 Testing Memory Models 301

17.6 Summary

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