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Continuing advances in chip technology, such as the ability to place more transistors on the same die (together with increased operating speeds) have opened new opportunities in embedded applications, breaking new ground in the domains of communication, multimedia, networking and entertainment. New consumer products, together with increased time-to-market pressures have created the need for rapid exploration tools to evaluate candidate architectures for System-on-Chip (SoC) solutions. Such tools will facilitate the introduction of new products customized for the market and reduce the time-to-market for such products. While the cost of embedded systems was traditionally dominated by the circuit production costs, the burden has continuously shifted towards the design process, requiring a better design process, and faster turn-around time. In the context of programmable embedded systems, designers critically need the ability to explore rapidly the mapping of target applications to the complete system. Moreover, in today's embedded applications, memory represents a major bottleneck in terms of power, performance, and cost. In particular, addresses efficient exploration of alternative memory architectures, assisted by a "compiler-in-the-loop" that allows effective matching of the target application to the processor-memory architecture. This new approach for memory architecture exploration replaces the traditional black-box view of the memory system and allows for aggressive co-optimization of the programmable processor together with a customized memory system. The book concludes with a set of experiments demonstrating the utility of this exploration approach. The authors perform architecture and compiler exploration for a set of large, real-life benchmarks, uncovering promising memory configurations from different perspectives, such as cost, performance and power. Moreover, the authors compare the Design Space Exploration heuristic with a brute force full simulation of the design space, to verify that the heuristic successfully follows a true pareto-like curve. Such an early exploration methodology can be used directly by design architects to quickly evaluate different design alternatives, and make confident design decisions based on quantitative figures. is designed for different groups in the embedded systems-on-chip arena. First, the book is designed for researchers and graduate students interested in memory architecture exploration in the context of compiler-in-the-loop exploration for programmable embedded systems-on-chip. Second, the book is intended for embedded system designers who are interested in an early exploration methodology, where they can rapidly evaluate different design alternatives, and customize the architecture using system-level IP blocks, such as processor cores and memories. Third, the book can be used by CAD developers who wish to migrate from a hardware synthesis target to embedded systems containing processor cores and significant software components. CAD tool developers will be able to review basic concepts in memory architectures with relation to automatic compiler/simulator software toolkit retargeting. Finally, since the book presents a methodology for exploring and optimizing the memory configuration for embedded systems, it is intended for managers and system designers who may be interested in the emerging embedded system design methodologies for memory-intensive applications.

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